Intel MCS BASIC-52 port to ARM M4 project

First posted
Thursday March 21, 2019 14:45
Updated
Tuesday April 29, 2019 11:02

Why project?

Wrote book on software technology.

Recent pdf. 1990 book!



Embedded controller software interactive metacompileable RTOS technology not c/c++.

Apps order of magnite[s?] more reliable than than c/c++ apps.

Thursday March 21, 2019 14:45



Dislike c/c++ programming enviroment.

Felt like Microsoft grunt on Windows 2000 project.

Lost control of project.

Metacompiler technolgy starts with an interactive RTOS produced from source.

App layered on top of RTOS.

Short app modules debugged, then added to RTOS and metacompiled.

App becomes part of the RTOS.

Incremental devlopement opposed to BUILD solution.

When app complete, then parts of the RTOS not used can be commented-out, then
remetacompiled leaving only the app ... if desired.
Did this with Intel 8085 NSA Missile Secure Cryotographic Unit in mid 1980s.
App written calling modules written in c/c++/masm to try to minimized code written, in this case INtel MCS BASIC-52., the RTOS high-level/incremental assembler.
Forth86 makes int 21 calls to DOS so to avoid duplicated code development.

$130 Asus E203MAS/hotmetal post.
But we adopt vb dot net.
vb dot net file reads.

4/2/19
vb dot net is not an RTOS.

Intel MCS BASIC=52 is an interactive RTOS capable of 2^n-bit extension.

Supports ARM M4 ASSEMBLER implementation in high-level BASIC52!

Metacompiler RTOS generation possible. RTOS generates itself from source.

iIntel MXC BASIC-52 RTOS Swarm = lots running on one machine/mjltipled machines commjunicating.

Notes

Tuesday April 29, 2019 10:55

Which Intel MCS BASIC-52 require port implemention?
2.1 RUN.·........................................................ 13 yes
2.2 CONT ....................................................... 14 yes
2.3 LiST.......................................................... 15 yes
2.4 LIST#........................................................ 16 yes
2.5 LIST@........................................................ 17 yes
2.6 NEW.......................................................... 18 yes
2.7 NULL


3.1 RAM and ROM................................... . . . . . . . . . . . . . . . . . 21 ?
3.2 XFER.................................................................................. 22 ?
3.3 PROG................................................................................. 23 ?
3.4 PROG 1 and PROG2 . . . . . . . . . . . . . . . . . . . . . ................... 24 ?
3.5 FPROG, FPROG1 and FPROG2 .................................. ; . . . . .. 25 ?
3.6 PROG3, PROG4, FPROG3, and FPROG4 (Version 1.1 only)....... .. 26 ?
3.7 PROG5, PROG6, FPROG5, and FPROG6 (Version 1.1 only) .. . . .. 27 ?

CHAPTER 4 Description of Statements
4.1 BAUD.................................................................. 28
4.2 CALL................................................................... 29
4.3 CLEAR................................................................. 30
4.4 CLEARS and CLEAR I . . . . . . . . . . . . . . . . . . . . ..... 31
4.5 CLOCK1 and CLOCKO ............................................ 32
4.6 DATA - READ - RESTORE . . . . . . . . . . . . . . . . . . . . 33
4.7 DIM.................................................................... 35
4.8 DO - UNTIL. . . . . . . . . . . . . . . . . . . . . . . . . . .......36
4.9 DO - WHILE ................................................. .......37
4.10 END.................................................................. 38
4.11 FOR-TO-STEP-NEXT ............................................ 39
4.12 GOSUB - RETURN. . . . . . . . . . . . . . . . . . . . . . .... 41
4.13 GOTO......................................... . . . . . . .......... 43
4.14 ON GOTO - ON GOSUB . . . . . . . . . . . . . . . . . . . .. 44
4.15 IF - THEN - ELSE.. . . . . . .. . . . . . . . . . .. . . . ...... 45
4.16 INPUT................................................................ 49
4.17 LET . . . . . . . . . . . . . . . . . . . . . . . . . . . . ............49
4.18 ONERR. . . . . . . . . . . . . . . . . . . . . . . . . . . ..........50
4.19 ONEXT1·......... . . . . . . . . . . . . . . . . . . . . . ......... 51
4.20 ONTIME ....................................... '.....................52
4.21 PRINT.:...............................................................54
4.22 PRINT# ............................. ' .' . . . . . . .......... . . .57
4.23 PHO., PH1., PHO. #, PH1. # . . . . . . . . . . . . . . . . . 58
4.24 PRINT@, PHO.@, PH1.@ (Version 1.1 Only). . . . . . . 59
4.25 PUSH...................................................................61
4.26 POP.................................................................... 61
4.27 PWM................................................................... 62
4.28 REM.................................................................... 63
4.29 RETI.... . . . . . . . . . . . . . . . . . . . . . . . . .............. 64
4.30 STOP . . . . . . . . . . . . . . . . . . . . . . . . . . .. ...........65
4.31 STRING . . . . . . . . . . . . . . . . . . . . . . . . . .. ..........66
4.32 UI1 AND UIO . . . . . . . . . . . . . . . . . . . . . . . ........ 67
4.33 U01 and UOO . . . . . . . . . . . . . . . . . . . . . . . ....... 68
4.34 IDLE (Version 1.1 only) . . . . . . . . . . . . . . . . . .. ....69
4.35 RROM (Version 1.1 only). . . . . . . . . . . . . . . . . ......70
4.36 LD@ and ST@ (Version 1.1 only) . . . . . . . . . . . . . . 71
4.37 PGM (Version 1.1 only) . . . . . ...............................71

Visual studio 2017, vb dot net $130 Asus E203 success ... after avoding both software bugs.





Friday April 19, 2019 11:27



Flex 6/hotmetal post after KB4493464 uninstall.

 

Visual Studio 2019 Lenovo Ideapd 320 core i5-7200U win 10/1809 7 fen.



Gives error message on invalid file path. 2017 did not.



Friday April 12, 2019 11:57

dot net perls file write code did not work on $130 Asus E203MAS 4/11/19.

No Myfile.txt.

Worked for about 4 hours.

Added call to Main(), message box. Gave up.

Copied code to fash to try on Flex 6.

Tried 4/12, Worked!







Lerning vb dot net and Visual studio 2107.

Build steps scary, imo.



vb dot net coding starts. :)
Using most high tech software tools to get ARM M4 assembler/Intel MCS BASIC-52 RTOS project working.
4/10/19

$130 Asus E203MAS Celeron N4000 [14 nm technology] used to enter and test about Visual Studio 2017/vb dot net code. Win 10/11803.

$800 Lenovo Flex 14 [aka 6] core i7-8550U also used to test code.

Can swarm $130 but not $800 laptops.
4/11/19

ARM Instruction Set.

Ongosub 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Column
0 x x x x 0 0 I y y y y S z z z z w w w w 0 0 0 1 0 0 0 1 0 0 0 0 Data Processing/PSR Transfer
1 x x x x 0 0 0 0 0 0 A S y y y y z z z z v v v v 1 0 0 1 u u u u Multiply
2 x x x x 0 0 0 0 0 U A S y y y y z z z z v v v v 1 0 0 1 u u u Multiply Long
3 x x x x 0 0 0 1 0 B 0 0 y y y y z z z z 0 0 0 0 1 0 0 1 u u u u Single Data Swap
4 x x x x 0 0 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 y y y y Branch and Exchange
5 x x x x 0 0 P U 1 B W L x x x x y y y y u u u u 1 S H 1 z z z z Halfword Data Transfer: register offset
6 x x x x 1 0 0 P U 1 W L y y y z z z z u u u u 1 S H 1 v v v v Halfword Data Transfer: immediate offset
7 x x x x 0 1 I P U B W L y y y y z z z z 0 0 1 0 0 0 0 1 0 0 0 0 Single Data Transfer
8 x x x x 0 1 1                                       1         Undefined
9 x x x x 1 0 0 P U D W L x x x x  0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 Block Data Transfer
10 x x x x 1 9 1 L 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 Branch
11 x x x x 1 1 0 P U N W L x x x x y y y y z z z z 0 0 0 1 0 0 0 0 Coprocessor Data Transfer
12 x x x x 1 1 0 P U N W L x x x x y y y y z z z z 0 0 0 1 0 0 0 0 Coprocessor Data Operation
13 x x x x 1 1 0 P U N W L x x x x y y y y z z z z 0 0 0 1 0 0 0 0 Coprocessor Register Transfer
14 x x x x 1 1 1 0 x x x L x x x x y y y y z z z z u u u 1 v v v v Software Interrupt
15                                                                  
  3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
Modified 4/10/19




Note Some instruction codes are not defined but do not cause the Undefined instruction trap to be taken, for instance a Multiply instruction with bit 6 changed to a 1. These instructions should not be used, as their action may change in future ARM implementations.
 

4.5 Data Processing.

Destination register `15-12

1st operand register 19-16

Set condition codes
0 = do not alter condition codes
1 = set condition codes
Operation Code 23-11

0000 = AND - Rd:= Op1 AND Op2
0001 = EOR - Rd:= Op1 EOR Op2
0010 = SUB - Rd:= Op1 - Op2
0011 = RSB - Rd:= Op2 - Op1
0100 = ADD - Rd:= Op1 + Op2
0101 = ADC - Rd:= Op1 + Op2 + C
0110 = SBC - Rd:= Op1 - Op2 + C
0111 = RSC - Rd:= Op2 - Op1 + C
1000 = TST - set condition codes on Op1 AND Op2
1001 = TEQ - set condition codes on Op1 EOR Op2
1010 = CMP - set condition codes on Op1 - Op2
1011 = CMN - set condition codes on Op1 + Op2
1100 = ORR - Rd:= Op1 OR Op2
1101 = MOV - Rd:= Op2
1110 = BIC - Rd:= Op1 AND NOT Op2
1111 = MVN - Rd:= NOT Op2

Immediate Operand 25

0 = operand 2 is a register

Shift 11-4 shift applied to Rm

Rm 3-0 2nd operand register


1 = operand 2 is an immediate value

Rotate 11-8 shift applied to Imm

Imm 7-0 Unsigned 8 bit immediate value

Condition field 

4.5.1 CPSR flags.

AND 0000 operand1 AND operand2
EOR 0001 operand1 EOR operand2
SUB 0010 operand1 - operand2
RSB 0011 operand2 - operand1
ADD 0100 operand1 + operand2
ADC 0101 operand1 + operand2 + carry
SBC 0110 operand1 - operand2 + carry - 1
RSC 0111 operand2 - operand1 + carry - 1
TST 1000 as AND, but result is not written
TEQ 1001 as EOR, but result is not written
CMP 1010 as SUB, but result is not written
CMN 1011 as ADD, but result is not written
ORR 1100 operand1 OR operand2
MOV 1101 operand2(operand1 is ignored)
BIC 1110 operand1 AND NOT operand2(Bit clear)
MVN 1111 NOT operand2(operand1 is ignored)



Destination register 15-12

1st operand register 19-16

Set condition codes 20
0 = do not alter condition codes
1 = set condition
Operation Code 24-21
0000 = AND - Rd:= Op1 AND Op2
0010 = SUB - Rd:= Op1 - Op2
0011 = RSB - Rd:= Op2 - Op1
0100 = ADD - Rd:= Op1 + Op2
0101 = ADC - Rd:= Op1 + Op2 + C
0110 = SBC - Rd:= Op1 - Op2 + C + 1
0111 = RSC - Rd:= Op2 - Op1 + C + 1
1000 = TST - set condition codes on Op1 AND Op2
1001 = TEQ - set condition codes on Op1 EOR Op2
1010 = CMP - set condition codes on Op1 - Op2
1011 = CMN - set condition codes on Op1 + Op2
1100 = ORR - Rd:= Op1 OR Op2
1101 = MOV - Rd:= Op2 1110 = BIC - Rd:= Op1 AND NOT Op2
1110 = BIC - Rd:= Op1 AND NOT Op2
1111 = MVN - Rd:= NOT Op2

Immediate Operand 21
0 = operand 2 is a register

Shift 11-4
shift applied to Rm
Rm 3-0
2nd operand register

1 = operand 2 is an immediate value
Rotate 11-8
shift applied to Imm
Imm 7-0
Unsigned 8 bit immediate value

4.5.2 Shifts.

11 7 6 5 4 11 8 7 6 5 4

Shift type 6 5.
00 = logical left
01 = logical right
10 = arithmetic right
11 = rotate right
Shift amount 11-7,
unsigned integer5 bit.


Shift type
00 = logical left
01 = logical right
10 = arithmetic right
11 = rotate right
Shift register 11-8.

Shift amount specified in
bottom byte of Rs

contents of Rm 31-0. carry out 27.

value of operand 2 26-0 6-0 0s.
Figure 4-6: Logical shift left

contents of Rm 31-0. 3. carruout 4

value of operand 2 31-5 31-27 0s
Figure 4-7: Logical shift right

contents of Rm 3130-0. 31 uplicated 6 times.

value of operand 25-5.
Figure 4-8: Arithmetic shift right


contents of Rm. 31-0

value of operand 2



Figure 4-10: Rotate right extended.

Register specified shift amount Only the least significant byte of the contents of Rs is used to determine the shift amount. Rs can be any general register other than R15. If this byte is zero, the unchanged contents of Rm will be used as the second operand, and the old value of the CPSR C flag will be passed on as the shifter carry output. If the byte has a value between 1 and 31, the shifted result will exactly match that of an instruction specified shift with the same value and shift operation. If the value in the byte is 32 or more, the result will be a logical extension of the shift described above:
1 LSL by 32 has result zero, carry out equal to bit 0 of Rm.
2 LSL by more than 32 has result zero, carry out zero.
3 LSR by 32 has result zero, carry out equal to bit 31 of Rm.
4 LSR by more than 32 has result zero, carry out zero.
5 ASR by 32 or more has result filled with and carry out equal to bit 31 of Rm.
6 ROR by 32 has result equal to Rm, carry out equal to bit 31 of Rm.
7 ROR by n where n is greater than 32 will give the same result and carry out as ROR by n-32; therefore repeatedly subtract 32 from n until the amount is in the range 1 to 32 and see above.
Note The zero in bit 7 of an instruction with a register controlled shift is compulsory; a one in this bit will cause the instruction to be a multiply or undefined instruction.

4.5.3 Immediate operand rotates

4.5.4 Writing to R15.

4.5.5 Using R15 as an operand.

4.5.6 TEQ, TST, CMP and CMN opcodes.

4.5.8 Assembler syntax.

4.5.9 Examples.

4.6 PSR Transfer (MRS, MSR).

4.6.1 Operand restrictions.

4.6.2 Reserved bits.

4.6.4 Assembler syntax.

4.6.5 Examples.

4.7 Multiply and Multiply-Accumulate (MUL, MLA).


4/10/19

Poster